The effort to build integrated circuits with more and faster semiconductor devices has a resulted in a continued shrinking of the devices within an integrated circuit. This corresponds to a reduction in the size and spacing of the individual transistors and interconnections in an integrated circuit. In many applications, the switching speed and size of the switching devices are functions of the critical dimension of the MOS transistor gate and interconnections to each device. Narrower or smaller device geometries tend to produce a higher performance or faster switching transistor. For example, in circuits having MOS switching devices, a very important process step is the formation of the gate for each transistor and the formation of the interconnection paths to connect each device to form, for example, a processor integrated circuit.
The continued reduction in integrated circuit geometry sizes improves the functionalities and pricing of the integrated circuit, however, the reduction in geometry sizes continues to challenge process designers and manufacturers. The limitations of conventional lithographic techniques used to pattern transistor gates and interconnects are quickly being realized. Accordingly, there is a continuing need for more efficient and effective fabrication processes for forming transistor gates and interconnects that are smaller and/or exhibit higher performance.
In conventional lithographic techniques, the surface of a silicon substrate wafer is coated with a light sensitive photoresist material. Once the photoresist material is formed on the surface of the silicon substrate, the wafer is aligned and the photoresist is exposed using a photo mask and a high intensity light source. The photo resist is developed, and the excess or unwanted photo resist is removed. The remaining photo resist forms a patterned mask over the surface of the silicon substrate, and is usually subjected to a baking or heating process to harden the photoresist and improve its adhesion to the surface of the underlying substrate. The patterned photoresist mask then allows the silicon surface to be exposed to an etching compound to form the features of the switching devices and interconnects in the integrated circuit.
The patterned mask has characteristic qualities and limitations with regard to its ability to maintain a uniform thickness across the substrate wafer, its adhesion qualities to the substrate surface, and its ability to uniformly maintain critical dimensions transferred to it through the formation, mask exposure, development, baking, and etch processes. Design and process engineers must weigh a multitude of factors in reducing the critical dimensions in the fabrication process. Factors relating to the photoresist include thickness uniformity, the ability to hold a pattern, proximity effects during the baking process, and etch resistance. These factors and others effectively define the resolution limit of the photoresist materials.
A critical dimension in the photoresist that is narrower than the photoresist resolution limit is generally incapable of providing an effective mask in the fabrication of a gate or interconnect. The results of using narrow dimensions beyond the resolution limit of the photoresist includes pattern collapse, bending, and pattern closures caused by proximity effects during the baking or reflow process. In addition, attempts to reduce the critical dimension by heating the resist to reflow, results in resist openings closing where openings are less dense or isolated in the resist mask pattern.
In particular in the example shown in FIG. 1A, the structure 100, is based on a substrate 110, the dielectric layer 120, and a photoresist layer that has been subjected to the normal spin, exposure, development, and wash processes 130. The photoresist mask 130, contains an opening 150, and 151, in close proximity and an isolated opening 152. In a standard procedure following the exposure and development of a photoresist a baking step is normally used to harden the photoresist and to improve adhesion to the surface of the substrate. Heating the resist material to reflow might be used to reduce the critical dimension of the photoresist pattern. However, holes and line patterns in the photoresist do not shrink or expand at the same rate. Heating the photoresist to reflow causes the resist to migrate at a rate that is difficult to control and some openings in the photoresist layer close. The problem also occurs when the density of openings varies. In areas of the photoresist mask where holes are isolated, the proximity effect and the photoresist reflow causes the isolated opening to collapse and close. This is illustrated in FIG. 1B showing an isolated opening 162 that has closed while resist openings 160 and 161 do not collapse. The loss of the opening 162 is an unacceptable result.